System Level Design from HW/SW to Memory for Embedded Systems System Level Design from HW/SW to Memory for Embedded Systems
IFIP Advances in Information and Communication Technology

System Level Design from HW/SW to Memory for Embedded Systems

5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3–6, 2015, Proceedings

Marcelo Götz and Others
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Publisher Description

This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015.

The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.

GENRE
Computing & Internet
RELEASED
2018
16 April
LANGUAGE
EN
English
LENGTH
243
Pages
PUBLISHER
Springer International Publishing
SELLER
Springer Nature B.V.
SIZE
4.6
MB

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