Fujitsu Laboratories Develops Power-Saving CMOS Technology for 32Nm-Generation and Beyond

Kawasaki, Dec 16, 2008 - (JCN Newswire) - Fujitsu Laboratories Limited announced today the development of power-saving CMOS technology(1) for logic LSI chips for 32 nanometer- (32nm-) generation and beyond. The new technology enables employment of a specific silicon crystal surface(2), which previously had not been applied in silicon substrates due to the crystal surface's conventionally low performance in the past, by improving its performance. As a result, as a world's first, the technology makes it possible to use current 45nm-generation fabrication facilities to reduce LSI power voltage without lowering operation speed, thereby containing production costs and cutting LSI power consumption during operation by approximately 20 percent (20%). It is anticipated that the technology can be used in a wide range of applications, such as system LSIs for various mobile devices that will need to be increasingly multi-functional, and for microprocessors of which many are running with multiple processing cores. Details of the technology were presented at the 2008 IEEE International Electron Devices Meeting (IEDM) being held from December 15 to 17 in San Francisco. (Session/Presentation 3.3)