Why It is Necessary to Change the IC ESD Target Specification Levels: After 20 "Static" Years, More Realistic Measures are Needed

In the late 1970s, with the advent of large-scale integration (LSI), ESD started to become a problem. Electronics manufacturing companies soon started to implement ESD control programs. At first, there was little information sharing and no ESD control standardization. Early standards focused on ESD risks from people and on ESD protective packaging. Standards for ESD control items, such as wrist straps, work surfaces and flooring followed as improvements to ESD control materials and equipment were made. In 1999, the ANSI/ESD S20.20-1999 standard for ESD process control was published. A third-party certification program was established to demonstrate compliance with the standard. Eight years later, updated versions of the ANSI/ESD S20.20-2007 and IEC 61340-5-1:2007 standards were published. Facilities compliant with these standards expect to be able to handle devices down to 100V for the Human Body Model (HBM) without significant problems. In this context, adding ESD protection to bring device ESD withstand to 2kV HBM seems to be a case of over-engineering. In the early days, devices had relatively small numbers of pins and were assembled largely using manual processes in relatively uncontrolled ESD environments. The likelihood of large amplitude HBM ESD events occurring to pins was relatively high. Over time, the number of device pins has increased dramatically, as has the level of manufacturing automation. Many devices can only be assembled in automated manufacturing systems, and ESD control has greatly improved. The likelihood of large amplitude HBM ESD has significantly reduced in these manufacturing processes. However, the number of protection networks required, and chip area they occupy, has grown along with pin count. Device ESD susceptibility test time and difficulty has increased correspondingly. When devices fail to meet the targets, the price of redesign can mean months of delay to product introduction. The ESD targets are particularly difficult to meet on high performance (e.g., low leakage or high-speed) pins. ESD protection networks add capacitance and leakage paths. At 45 nm and 32 nm technology, 18 Gb/s cannot be met with 2kV ESD protection, but can be with 1kV or less.